Title: VOLTAGE HARMONIC REDUCTION WITH CAPACITIVE LOADS USING SYNCHRONOUS REFERENCE FRAME WITH SPACE VECTOR PULSE WIDTH MODULATION
Authors: Sijuwade Akintade, Patience Akawu

Research Area: Engineering

Date Published: 26-08-2024

Abstract

Harmonics caused by capacitive loads was considered using the developed SAPF. The current harmonics are being caused by nonlinear characteristic of electronics based equipments which increase power losses and in turn reduce power quality. Switching signal generation was done using SVPWM. With RC load under balanced input voltage condition, the developed SAPF-SVPWM achieved a reduction of THD of 1.35% as compared to 35.46 before compensation. In addition, the developed SVPWM model was compared with SAPF without compensation using RC load under unbalanced voltage and the result shows that the developed SVPWM achieved reduction in THD of 3.01% as compared to 41.83% after and before compensation. The developed SVPWM model was also compared with SPWM for balanced and unbalanced input voltage condition. The results reveal that SVPWM performed better than SPWM. All the results obtained are within IEEE 519 harmonics limits with capacitive loads under balanced and unbalanced voltage.